In recent years, for a wireless integrated circuit used for a wireless LAN (Local Area Network) or the like, a demand for miniaturizing the entire system by integrating a baseband function and a wireless function on one chip is increasing. In the case of increasing the integration degree of a semiconductor chip, increase in the chip area has to be suppressed by using microfabrication process. However, in the case of using microfabrication process, problems such as largo variations in the threshold of a transistor and large variation in circuit characteristics occur. To address the problems, patent literature 1 discloses a technique of suppressing variations in a jitter value caused by manufacture variations in a PLL circuit. In the patent literature 1, variations in a jitter value are suppressed by using a gain adjustment circuit for adjusting the gain of a voltage controlled oscillator in a PLL circuit and an offset adjustment circuit for stopping an offset control signal for controlling the oscillation frequency of an output signal of the voltage controlled oscillator when a control voltage of a predetermined value is applied to become a target value.